Gabriele Serra

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• R&D Engineer @ Accelerat
• Professional Affiliate @ Scuola Superiore Sant'Anna
• Qualified software engineer

TL;DR

Introducing myself

I am an R&D Engineer in the safety and security Team at Accelerat, a spin-off company of the Scuola Superiore Sant'Anna of Pisa, where I held a Postdoctoral position.

My duties include the design and implementation of system software (kernel, firmware, hypervisors) for real-time safety-critical systems, taking advantage of modern SoCs features (crypto core, virtualization, hw-sw codesign) to enhance the safety and security of the entire system.

Bio

In October 2023, I received a PhD in Emerging Digital Technologies for Embedded Systems at the Real-Time Systems (ReTiS) Laboratory of the Scuola Superiore Sant'Anna, where I was an industrial PhD Student working under the supervision of Prof. Giorgio Buttazzo and Prof. Alessandro Biondi.

In June 2019, I received a Master's degree in Embedded Computing Systems, a course offered jointly by Università di Pisa & Scuola Superiore Sant'Anna. I graduated cum laude with a thesis on IPC mechanisms and exception handling for an RT safety-critical kernel, sponsored by Rete Ferroviaria Italiana.

In 2022, I visited the Systems Research and Architecture (SRA) group at Leibniz Universität - Hannover (Germany), where I spent six months as a Doctoral Researcher in the group supervised by Prof. Daniel Lohmann.

I have been a co-founder and CTO at DeliveryAggregator, a company focused on last-mile logistics where I mainly led company development strategy on embedded and mobile systems.

Further, since 2022, I have been a Research Engineer at Accelerat, working on software solutions for safe, secure, and predictable cyber-physical systems.

Research

My research is focused on Operating Systems and Virtualization for Real-Time Embedded Systems. Particularly I'm working on:

• The role of virtualization in mixed-criticality systems
• Improvement of programming models for managing safety/security requirements
• Development of mechanism to avoid (or account) interference due to resource sharing

From the beginning of my career in the academic field, I served as:

• Web-chair of 2022 and 2023 RAGE Workshop
• Secondary reviewer for the following conferences and workshops: DSD (2023), ISORC (2022), RTAS (2022), EMSOFT (2022, 2021), RTCSA (2022), DAC (2021), WCFS(2021), ICCPS (2020), RTSS (2019), DETECT (2019)
• Reviewer for International journals:
  • Microprocessors and Microsystems: Embedded Hardware Design (MICPRO)
  • Real-Time Systems: The International Journal of Time-Critical Computing Systems (TIME)
  • ACM Transactions on Embedded Computing Systems (TECS)
  • Journal of Systems Architecture: Embedded Software Design (JSA)

Say Thanks

As a researcher, I strongly support open knowledge and open-source software. I really focus my effort on publishing stuff and always keep it free and available. Then, if you like something that I published or just want to support my activities, buy me a beer!

Counters